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[OS program] 8086IP

Description: 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
Platform: | Size: 71680 | Author: 林丹 | Hits:

[VHDL-FPGA-Verilog] can.tar

Description: can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
Platform: | Size: 54272 | Author: yu | Hits:

[Other Embeded program] cyc2_cmon_080805

Description: Verilog 8051 IP Core for Cyclone -Verilog 8051 IP Core for Cyclone II
Platform: | Size: 63488 | Author: Alx | Hits:

[VHDL-FPGA-Verilog] USB2.0IP

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档-Complete Verilog language developed by USB2.0 IP core source code, including documentation
Platform: | Size: 206848 | Author: 陈润 | Hits:

[VHDL-FPGA-Verilog] CAN_IP

Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[SCM] DW8051(Verilog)

Description: 51单片机IP核源码，可以在fpga实现，并进行仿真与验证-51 single-chip IP nuclear source, you can achieve the fpga, and simulation and verification
Platform: | Size: 67584 | Author: xuhuifeng | Hits:

[VHDL-FPGA-Verilog] VERILOG-USB2.0IP-core

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files
Platform: | Size: 220160 | Author: king | Hits:

[VHDL-FPGA-Verilog] 10100MIP

Description: 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码，可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
Platform: | Size: 740352 | Author: 打狗队 | Hits:

[Crack Hack] aes_core

Description: aes_core verified verilog ip core-aes_core verified verilog ip core
Platform: | Size: 11264 | Author: 邓婕 | Hits:

[VHDL-FPGA-Verilog] FFT_verilog

Description: verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
Platform: | Size: 618496 | Author: culun | Hits:

[Post-TeleCom sofeware systems] qam_64

Description: 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
Platform: | Size: 1024 | Author: zhujing | Hits:

[VHDL-FPGA-Verilog] 8051_verilog

Description: 8051 IP, 使用veriog实现，在Altera9.0环境下编译通过-8051 IP in verilog, which is verified in Altera9.0 environmen.
Platform: | Size: 51200 | Author: dylan huang | Hits:

[ARM-PowerPC-ColdFire-MIPS] arm7verilog

Description: ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
Platform: | Size: 1400832 | Author: zdh | Hits:

[Embeded-SCM Develop] ARMcore

Description: 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
Platform: | Size: 690176 | Author: 王钊 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP(RTL)

Description: USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
Platform: | Size: 64512 | Author: AmazingEric | Hits:

[VHDL-FPGA-Verilog] sd_slave_device

Description: verilog source code for SD card SLAVE DEVICE IP-Core
Platform: | Size: 15360 | Author: Antti Lukats | Hits:

[DSP program] IP

Description: this a programme about dsp ,it can achieve tcp/ip communication ,the programme is corect ,i wish that you can download it .-this is a programme about dsp ,it can achieve tcp/ip communication ,the programme is corect ,i wish that you can download it .
Platform: | Size: 75776 | Author: 小龙 | Hits:

[VHDL-FPGA-Verilog] wishbone

Description: wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
Platform: | Size: 13312 | Author: thegreeneyes | Hits:

[VHDL-FPGA-Verilog] cortex_m1

Description: cortex_m1 verilog IP，synplify环境-cortex_m1 verilog IP, synplify environment
Platform: | Size: 3679232 | Author: dpai | Hits:

[VHDL-FPGA-Verilog] verilog-usb--protel-design

Description: 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
Platform: | Size: 53248 | Author: 唐明桂 | Hits:
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